A communication device, such as a mobile phone, includes a voltage controlled oscillator as a local oscillator. The voltage controlled oscillator is required to have the accuracy of signal Generation (for example, quadrature signals which are 90° out of phase with each other), and in addition to this, a simpler circuit and lower power consumption for realizing a mobile system.
FIGS. 9 to 15 show conventional structures of an oscillator for generating a quadrature signal.
An oscillator (hereinafter referred to as a first conventional technique) shown in FIGS. 9(a) and 9(b) uses a voltage controlled oscillator (VCO), running at twice the frequency of the desired quadrature signals, and a divide-by-two circuit shown in FIG. 9(a). The divide-by-two circuit is usually a digital master-slave flip flop circuit. In the digital master-slave flip flop circuit, outputs Q and QB of a mater flip flop are connected with inputs D and DB of a slave flip flop, respectively, and outputs Q and QB of the slave flip flop are fed back to inputs DB and B of the master flip flop, respectively. Note that an oscillating signal (a signal having twice the frequency of the desired signal, see FIG. 9(b)) from the VCO is used as a CLK signal. Therefore, the outputs (Q and QB) of each flip flop are 180° out of phase, and the output Q (QB) of the master flip flop and the output Q (QB) of the slave flip flop are 90° out of phase (see FIG. 9(b)). That is, the output Q (QB) of the master flip flop can be used for an f signal, and the output Q (QB) of the slave flip flop can be used for a Q signal.
Moreover, oscillators (hereinafter referred to as a second conventional technique) disclosed in Patent Document 1 (U.S. Pat. No. 6,404,293 B1) and Non-Patent Document 1 (A. Rofougaran et al., “A 900 MHz CMOS LC oscillator with quadrature outputs,” Int. Solid-State Circuits Conference, San Francisco, Calif, 1996, pp. 316–317.) are arranged as follows.
As shown in FIG. 10, each of paired oscillator circuits A and B includes two coils, two capacitors, two N-channel MOS transistors cross-connected with each other, and a constant current source.
For example, in the oscillator circuit A, a coil 826 and a capacitor 827 are connected in parallel with each other between a high potential end power source and a drain terminal of an N-channel MOS transistor 818. Moreover, a coil 828 and a capacitor 829 are connected in parallel with each other between the high potential end power source and a drain terminal of an N-channel MOS transistor 820. Further, a gate terminal of the MOS transistor 818 is connected with the drain terminal of the MOS transistor 820, and a gate terminal of the MOS transistor 820 is connected with the drain terminal of the MOS transistor 818. Further, a source terminal of the MOS transistor 818 and a source terminal of the MOS transistor 820 are connected with a constant current source 810.
The oscillator circuits A and B are connected with each other via four MOS transistors (834, 836, 838 and 840). For example, a drain terminal of the N-channel MOS transistor 834 is connected with the drain terminal of the MOS transistor 818 of the oscillator circuit A, a gate terminal of the N-channel MOS transistor 834 is connected with a drain terminal of a MOS transistor 824 of the oscillator circuit B, and a source terminal of the N-channel MOS transistor 834 is connected with the constant current source. Moreover, a drain terminal of the N-channel MOS transistor 838 is connected with a drain terminal of a MOS transistor 822 of the oscillator circuit B, a gate terminal of the N-channel MOS transistor 838 is connected with the drain terminal of the MOS transistor 818 of the oscillator circuit A, and a source terminal of the N-channel MOS transistor 838 is connected with the constant current source.
Moreover, an oscillator (hereinafter referred to as a third conventional technique) disclosed in Patent Document 2 (U.S. Pat. No. 5,912,596) is arranged as follows.
As shown in FIG. 11, each of paired oscillator circuits A and B includes one P-channel MOS transistor, two coils, one variable capacitor, four N-channel MOS transistors and a constant current source.
For example, in the oscillator circuit A, a coil 52 is connected between a drain terminal of a P-channel MOS transistor 82 and an N-channel MOS transistor 76, and a coil 50 is connected between the drain terminal of the MOS transistor 82 and an N-channel MOS transistor 74. A source terminal of the MOS transistor 82 is connected with a Vdd, and a gate terminal of the MOS transistor 82 is connected with a bias. Moreover, a variable capacitor 56 is provided between a drain terminal of the MOS transistor 74 and a drain terminal of the MOS transistor 76. Further, a source terminal of the MOS transistor 74, a source terminal of the MOS transistor 76, a source terminal of a MOS transistor 72 and a source terminal of a MOS transistor 78 are connected with each other, and those are connected with the current source. Further, a drain terminal of the MOS transistor 72 is connected with a gate terminal of the MOS transistor 76, and a drain terminal of the MOS transistor 78 is connected with a gate terminal of the MOS transistor 74.
The oscillator circuits A and B are connected with each other via electrodes of eight MOS transistors (60, 62, 64, 66, 72, 74, 76 and 78) and two variable capacitors 46 and 48. For example, a gate terminal of the MOS transistor 78 of the oscillator circuit A is connected with a drain terminal of the MOS transistor 62 of the oscillator circuit B. A gate terminal of the MOS transistor 72 of the oscillator circuit A is connected with a drain terminal of the MOS transistor 64 of the oscillator circuit B. Moreover, two variable capacitors 46 and 48 are connected in parallel with each other between the drain terminal of the MOS transistor 74 and the drain terminal of the MOS transistor 64.
Moreover, an oscillator (hereinafter referred to as a fourth conventional technique) disclosed in Patent Document 3 (U.S. Pat. No. 6,639,481 B1) is arranged as follows.
As shown in FIG. 12, each of paired oscillator circuits A and B includes two P-channel MOS transistors cross-connected with each other, six variable capacitors, two N-channel MOS transistors cross-connected with each other, and a variable constant current source.
For example, in the oscillator circuit A, a source terminal of a P-channel MOS transistor 54 is connected with a source terminal of a P-channel MOS transistor 56, a gate terminal of the MOS transistor 54 is connected with a drain terminal of the MOS transistor 56, and a gate terminal of the MOS transistor 56 is connected with a drain terminal of the MOS transistor 54. Moreover, a source terminal of an N-channel MOS transistor 58 is connected with a source terminal of the N-channel MOS transistor 60, and those are connected with a constant current source 62. Further, a gate terminal of the MOS transistor 58 is connected with a drain terminal of the MOS transistor 60, and a gate terminal of the MOS transistor 60 is connected with a drain terminal of the MOS transistor 58. Moreover, the drain terminal of the MOS transistor 56 is connected with the drain terminal of the MOS transistor 60, and the drain terminal-of the MOS transistor 54 is connected with the drain terminal of the MOS transistor 58. Moreover, two variable capacitors 64 and 66 are serially connected with each other between the drain terminal of the MOS transistor 54 and the drain terminal of the MOS transistor 56. Moreover, four variable capacitors 68, 70, 72 and 74 are serially connected with each other between the drain terminal of the MOS transistor 54 and the drain terminal of the MOS transistor 56.
Two oscillator circuits A and B are connected with each other via two transformers 25 and 27. For example, the transformer 25 includes two windings, and one end of one winding is connected between the variable capacitors 68 and 70 in the oscillator circuit A, and another end of the winding is connected between the variable capacitors 72 and 74 in the oscillator circuit A. Moreover, one end of another winding is connected with a drain terminal of an N-channel MOS transistor 18 in the oscillator circuit B, and another end of the winding is connected with a drain terminal of an N-channel MOS transistor 20.
As shown in FIGS. 13, 14(a) to 14(d) and 15, Patent Document 4 (U.S. Pat. No. 6,456,167 B1) and Non-Patent Documents 2 (J. van der Tang, et al., “Analysis and design of an optimally coupled 5-GHz quadrature LC oscillator,” IEEE Journal of Solid-State Circuits, vol. 37, No. 5, May 2002, pp. 657–661.) and 3 (P. Andreani et al., “Analysis and design of a 1.8-GHz CMOS LC quadrature VCO,” IEEE Journal of Solid-State Circuits, vol. 37, No. 12, December 2002, pp. 1737–1747.) disclose an arrangement in which paired oscillators are connected with each other via MOS transistors.
However, the first conventional technique requires a VCO which runs at twice the desired frequency. On this account, the power consumption of the oscillator increases, and the circuit (flip flop circuit) design becomes complex.
Moreover, in the second and third conventional techniques and conventional techniques disclosed in Patent Documents 5 to 7, a large number of MOS transistors that are active elements are used for connecting two oscillator circuits with each other. On this account, noise (phase noise, etc.) is easily generated, and the power consumption increases. In addition, a circuit area increases.
Moreover, in the fourth conventional technique, the variable capacitors (varactors) and the transformers are used for connecting two oscillator circuits with each other. On this account, a circuit area increases, and the power consumption also increases.